In communication devices it is common to have multiple clocks or oscillators that provide clock signals of varying characteristics, including frequency, to device circuitry. In order for the device to operate properly, it is often necessary for certain device operations that operate at different clock frequencies to be synchronized. In order to accomplish this it is necessary to determine the frequency at which a clock operates in relation to a known, or predetermined, reference clock. This is typically done by counting, for a predetermined and known period of time, the number of cycles of a known reference clock having a known frequency, as well as the number of cycles of a second clock of unknown frequency.
A typical circuit for determining a ratio between two clock signals is shown in FIG. 11. This prior art circuit included a numerator latch 1 for receiving and storing the contents of an incrementing counter 7 when a load count signal LCS is received by the numerator latch 1. Incrementing counter 7 was clocked by a clock signal CLK 1. With each pulse of the clock signal CLK 1 the count value of the incrementing counter 7 increased by a value of one (1). There was also provided a denominator latch 4 which, upon receiving load count signal LCS, received and stored the contents of an incrementing counter 5. Incrementing counter 5 was clocked by a clock signal CLK 2. The count value controlling the incrementing counter 5 is increased by a value of one (1) with each pulse of the clock signal CLK 2. Upon receipt of the load count signal LCS, numerator latch 1 and denominator latch 4 made their respective values available for output as numerator out signal 8 and denominator out signal 9, respectively. In order to compute the ratio of the two clock signals CLK 1 and CLK 2, the values of the numerator out signal 8 and denominator out signal 9 were divided to produce the ratio between clock signals CLK 1 and CLK 2.
Where, for example, the frequency of CLK 1 was known, the ratio between the value of numerator latch 1 and denominator latch 4 can be used to compute the frequency of the clock signal CLK 2. This process was typically carried out as a part of a dedicated clock pulse count operation and was only as accurate as the resolution of the counting device allowed. The uncertainty in the resulting clock ratio measurement was proportional to the period of the slower clock and inversely proportional to the length of time over which the counts were accumulated. This typical ratio-counting device did not provide for dynamically increasing the accuracy of the count while counting the clock cycles. Thus, there is a need to address the deficiencies and inadequacies in the typical ratio-counting devices.